In recent optical communications systems, the transmission capacity is increased by raising the bit rate. On the other hand, when transmitting signals between internal modules such as a transmitting apparatus and a receiving apparatus or between integrated circuits (ICs) in an optical communications system, low-speed transmission or signal processing is generally performed by using not high-speed serial signals but parallel signals obtained by converting serial signals into a parallel form.
In transmission of parallel signals, the transmission rate per channel decreases as the number of parallel signal transmissions increases. This eases the high-speed characteristics required of a device, and also facilitates phase matching between channels. On the other hand, an increase in the number of parallel signal transmissions gives rise to such problems as an increase in the number of pins on ICs or modules, the resulting increase in the size of a package or the like, and an increase in the mounting area of transmission lines.
Currently, as a scheme for parallel transmission of signals at a bit rate of 40 Gbit/s, standardization of a scheme which performs transmission using four channels with a bit rate of 10 Gbit/s is underway. Furthermore, a scheme for parallel transmission of signals at 100 Gbit/s has been also proposed. However, an attempt to perform phase matching between channels at various locations in a parallel transmission interface leads to an increase in the circuit scale or power consumption of individual circuits including an optical transmitting-receiving circuit.
Accordingly, in the Multi-Lane Distribution (MLD) scheme of 40 Gbit/s and 100 Gbit/s Ethernet (registered trademark), phase shifts between channels (lanes) during transmission are tolerated, and phases are matched at once in the circuit at the receiving side.
FIG. 1 illustrates an exemplary configuration of such a parallel transmission system. The parallel transmission system in FIG. 1 includes Physical Coding Sublayer/Multi-Lane Distribution (PCS/MLD) circuits 101, 104, and Physical Medium Attachment/Physical Medium Dependent (PMA/PMD) circuits 102, 103. Of these, the PCS/MLD circuit 101 and the PMA/PMD circuit 102 are circuits at the transmitting side, and the PMA/PMD circuit 103 and the PCS/MLD circuit 104 are circuits at the receiving side.
The PCS/MLD circuits 101, 104 are connected to a layer above the Media Access Interface (MAC) layer by 100G Medium Independent Interface/40G Medium Independent Interface (CGMII/XLGII). In addition, the PCS/MLD circuits 101, 104 and the PMA/PMD circuits 102, 103 are connected by 100G Attachment Unit Interface/40G Attachment Unit Interface (CAUI/XLAUI). Further, the PMA/PMD circuit 102 and the PMA/PMD circuit 103 are connected by a link (transmission path) of m channels.
The CGMII/XLGMII is a logical interface within a chip. The CAUI/XLAUI is an electrical interface between chips. If the number of channels between the PCS/MLD circuits and the PMA/PMD circuits is N, N=4 in the case of 40 Gbit/s, and N=10 in the case of 100 Gbit/s.
The number m of channels for parallel transmission between the PMA/PMD circuit 102 and the PMA/PMD circuit 103 is not necessarily fixed. The number m of channels for parallel transmission between the PMA/PMD circuit 102 and the PMA/PMD circuit 103 varies such that the number of channels may be 4 or 10 even in the case of 100 Gbit/s. The number m of channels for parallel transmission between the PMA/PMD circuit 102 and the PMA/PMD circuit 103 may be 1.
The PMA/PMD circuit 102 converts parallel signals of N channels outputted from the PCS/MLD circuit 101 into signals of m channels and outputs the signals to the transmission path. The PMA/PMD circuit 103 converts the signals of m channels received from the transmission path into parallel signals of N channels and outputs the parallel signals to the PCS/MLD circuit 104.
Skew as the difference in delay time between signals on individual channels can occur at the following locations in the parallel transmission system. (1) Within the PCS/MLD circuit 101: Transmitting-side PCS skew (2) Between the PCS/MLD circuit 101 and the PMA/PMD circuit 102: Transmitting-side electrical skew (3) Within the PMA/PMD circuit 102: Transmitting-side PMA/PMD skew (4) Between the PMA/PMD circuit 102 and the PMA/PMD circuit 103: Transmission skew (5) Within the PMA/PMD circuit 103: Receiving-side PMA/PMD skew (6) Between the PMA/PMD circuit 103 and the PCS/MLD circuit 104: Receiving-side electrical skew (7) Within the PCS/MLD circuit 104: Receiving-side PCS skew
Since each of the skews (1) to (7) mentioned above is accumulated at the receiving side, it is desirable to correct the accumulated skew in the PCS/MLD circuit 104.
FIG. 2 illustrates a method of correcting skew accumulated in the case of N=m=4. The PCS/MLD circuit 101 at the transmitting side splits a bit string to be transmitted into blocks of predetermined size (1, 2, 3, 4, . . . ) and periodically divides the blocks among four channels for output as parallel signals. At this time, the PCS/MLD circuit 101 inserts an alignment block A for skew measurement at the beginning of each channel. In the proposed scheme, the block size is 66 bits, of which 2 bits are used as a header.
The PCS/MLD circuit 104 at the receiving side detects the alignment blocks A of the four channels, and corrects skew by a deskew circuit (not shown) to align the blocks of the four channels. The detected alignment blocks A are deleted.
A typical skew compensation circuit is selects a delay time for skew compensation by switching outputs of a delay circuit by a switching circuit.
A typical skew compensation apparatus is detects an amount of skew in each channel at a timing determined on the basis of a frame signal generated for each channel, and compensates for the timing of parallel data for each channel.
Typical systems are discussed in Japanese Laid-open Patent Publication No. 57-017046 and Japanese Laid-open Patent Publication No. 11-341102.
The parallel transmission systems according to the related art described above have at least the following problems.
If each of the skews (1) to (7) mentioned above is accumulated, a very large skew can occur in the PCS/MLD circuit 104 at the receiving side. For example, when the maximum values of the transmitting-side PCS skew, transmission skew, and receiving-side PCS skew are estimated to be 25 ns, 35 ns, and 15 ns, respectively, a skew of up to about 80 ns occurs in total. This amount of skew is equivalent to 800 UI (800 bits) in terms of a bit rate of 10 Gbit/s.
To ensure phase matching between channels by correcting 800 bits of skew, it is necessary to provide a First-In First-Out (FIFO) circuit of 1000 bits or more per channel. Provision of a First-In First-Out (FIFO) circuit of 1000 bits or more leads to an increase in the circuit scale or power consumption of a deskew circuit.
The same problem occurs not only in the case of MLD scheme of 40 Gbit/s and 100 Gbit/s but also in cases when skew is accumulated in a parallel transmission system in which parallel data signals are transmitted. This problem does not depend upon whether the transmission path between the transmitting apparatus and the receiving apparatus is an optical transmission path or not.
An object of an embodiment of the present invention is to avoid an increase in a circuit scale of a deskew circuit including in a parallel transmission system which transmits parallel data signals including a plurality of channels.